Materials &
Integration

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”

—Gordon Moore, 1965

Can the integration of unconventional materials enhance conventional silicon circuits and continue the progress traditionally associated with scaling?

Page 3

Three Dimensional Monolithic System-on-a-Chip (3DSoC)

The overall goal of the Three Dimensional Monolithic System-on-a-Chip (3DSoC) program is to develop 3D monolithic technology that will enable > 50X improvement in System-on-a-Chip (SoC) digital performance at power. 3DSoC aims to drive research in process, design tools, and new compute architectures for future designs while utilizing U.S. fabrication capabilities. 

Foundations Required for Novel Compute (FRANC)

The goal of the Foundations Required for Novel Compute (FRANC) program is to define the foundations required for assessing and establishing the proof of principle for beyond von Neumann compute architectures. FRANC will seek to demonstrate prototypes that quantify the benefits of such new computing architectures.

Foundational ERI

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

To enhance overall system flexibility and reduce design time for next-generation products, the Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS) program seeks to establish a new paradigm in IP reuse. CHIPS envisions an ecosystem of discrete modular, reusable IP blocks that can be assembled into a system using existing and emerging integration technologies. Modularity and reusability of IP blocks will require electrical and physical interface standards to be widely adopted by the community supporting the CHIPS ecosystem. Therefore, the program will develop the design tools and integration standards required to demonstrate modular integrated circuit (IC) designs that leverage the best of DoD and commercial designs and technologies.