“Perhaps newly devised design automation procedures could translate from logic diagram to technological realization with any special engineering.”

—Gordon Moore, 1965

Can we dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialization and innovation?

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Intelligent Design of Electronic Assets (IDEA)

The overall goal of the Intelligent Design of Electronic Assets (IDEA) program is to create a “no human in the loop” layout generator that enables users with no electronic design expertise to complete the physical design of electronic hardware within 24 hours. IDEA plans to develop the algorithms, methodologies, and software required to create an automated, unified layout generator for mixed-signal integrated circuits, systems-in-package, and printed circuit boards. 

POSH Open Source Hardware (POSH)

The overall goal of the Posh Open Source Hardware (POSH) program is to create an open source SoC design and verification ecosystem that will enable the cost effective design of ultra-complex SoCs. POSH seeks to create the hardware assurance technology required for signoff-quality validation of open source mixed signal SoCs, develop critical open source IP components, and demonstrate a high-performance open source SoC using the POSH ecosystem.

Real-Time Learning Machines (RTML)

A critical challenge in computing is the creation of processors that can proactively interpret and learn from data in real-time, apply previous knowledge to solve unfamiliar problems, and operate with the energy efficiency of the human brain. Competing challenges of low-SWaP, low-latency, and adaptability require the development of novel algorithms and circuits specifically for real-time machine learning. To address real time embedded system challenges, the National Science Foundation (NSF) and DARPA have teamed up to explore rapid development of energy efficient hardware and ML architectures that can learn from a continuous stream of new data in real time. The goal of the DARPA RTML program is to create a compiler that can take ML frameworks, like TensorFlow and Pytorch, as an input and generate optimized Verilog code for hardware implementation. The RTML compiler is expected to enable rapid prototyping and design space exploration for next wave AI hardware.

Foundational ERI

Circuit Realization at Faster Timescales (CRAFT)

The Circuit Realization at Faster Timescales (CRAFT) program seeks to shorten the design cycle for custom integrated circuits to months rather than years; devise design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository of innovations so that methods, documentation, and intellectual property can be repurposed, rather than reinvented, with each design and fabrication cycle. This novel design paradigm could help diversify the innovation ecosystem by making it practical for small design teams to take on complex custom circuit development challenges that are out of their reach today. Reducing the time and cost for designing and procuring custom, high-efficiency integrated circuits, should drive the technology community toward best commercial fabrication and design practices and enable a versatile development environment where designers make decisions based on the best technical solutions without worrying about circuit design delays or costs.