Architectures

“…we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array.”

—Gordon Moore, 1965

Can we enjoy the benefits of specialized circuitry while still relying on general programming constructs through the proper software/hardware co-design?

Phase II - Security

Guaranteed Architectures for Physical Security (GAPS)

Today’s system owners have few guarantees about where their private, proprietary, or security sensitive data resides or of its secure movement between systems. The Guaranteed Architectures for Physical Security (GAPS) program will develop hardware and software architectures that provably guarantee the security of high-risk transactions, where data moves between systems of different security levels. GAPS will develop hardware and software co-design tools that allow data separation requirements to be defined during system design as well as protections that can be physically enforced at system runtime. These verifiable security properties may help create safer commercial systems useful for preserving proprietary information and protecting consumer privacy.

Phase II - Defense Applications

Digital RF Battlespace Emulator (DRBE)

The Digital RF Battlespace Emulator (DRBE) program seeks to create a new breed of High Performance Computing (HPC) – dubbed “Real Time HPC” (RT-HPC) – that will effectively balance computational throughput with extreme low latency. DRBE will demonstrate RT-HPC domain-specific computing architectures by creating the world’s first largescale, virtual radio frequency (RF) test range, enabling more frequent and effective testing of RF systems. The DRBE test range will become a key part of DoD’s infrastructure, ushering in an era of system development and test based on 24/7/365 data generation. Commercial applications of RT-HPC are also expected, particularly in the area of big-data exploitation.

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Software Defined Hardware (SDH)

The goal of the Software Defined Hardware (SDH) program is to build runtime-reconfigurable hardware and software that enables near application-specific integrated circuit (ASIC) performance without sacrificing programmability for data-intensive algorithms. SDH aims to create a hardware/software system that allows data-intensive algorithms to run at near ASIC efficiency without the cost, development time, or single application limitations associated with ASIC development.

Domain-specific System on Chip (DSSoC)

The overall goal of the Domain-specific System on Chip (DSSoC) program is to develop a heterogeneous SoC comprised of many cores that mix general-purpose processors, special-purpose processors, hardware accelerators, memory, and input/output (I/O). DSSoC seeks to enable the rapid development of multi-application systems through a single programmable device.

Foundational ERI

Hierarchical Identify Verify Exploit (HIVE)

The Hierarchical Identify Verify Exploit (HIVE) program seeks to build a graph analytics processor that can process streaming graphs 1000X faster and at much lower power than current processing technology. If successful, the program will enable graph analytics techniques powerful enough to solve tough challenges in cyber security, infrastructure monitoring and other areas of national interest. Graph analytic processing that currently requires racks of servers could become practical in tactical situations to support front-line decision making. What’s more, these advanced graph analytics servers could have the power to analyze the billion- and trillion-edge graphs that will be generated by the Internet of Things, ever-expanding social networks, and future sensor networks.