July 23-25  |  San Francisco, CA

Monday, July 23, 2018

1:00 PM


2:30 PM

Welcome and Announcement of ERI "Page 3" Teams
Dr. Jay Lewis, Deputy Director, DARPA MTO

3:15 PM

Introduction of Joint University Microelectronics Program (JUMP) Focus Areas
Dr. Linton Salmon, Program Manager, DARPA MTO and presentations from each JUMP Center Director

4:30 PM

Science and Policy at the End of Moore's Law
Dr. Erica Fuchs, Professor, Department of Engineering and Public Policy at Carnegie Mellon University

5:00 PM

Impact of Commercial Partnership with the DoD
Mr. Tom Beckley, Senior Vice President & GM of Custom IC & PCB Group, Cadence Design Systems

5:30 PM

Reception and Networking

7:00 PM


Tuesday, July 24, 2018

7:00 AM

Registration and Breakfast

8:00 AM

Opening Remarks and Introduction
Dr. William Chappell, Director, DARPA MTO

8:05 AM

Dr. John Hennessy, Chairman, Alphabet

8:50 AM

The DARPA Mission
Dr. Steven Walker, DARPA Director

9:05 AM

The Electronics Resurgence Initiative
Dr. William Chappell, Director, DARPA MTO

9:35 AM


“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”
—Gordon Moore, 1965

Can the integration of unconventional materials enhance conventional silicon circuits and continue the progress traditionally associated with scaling?

10:00 AM

Materials and Integration Keynote – Device Technologies
Dr. Mike Mayberry, CTO, Intel

10:30 AM

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)

11:15 AM

Materials and Integration ("Page 3") – Three Dimensional Monolithic System-on-a-Chip (3DSoC)

12:00 PM

Materials and Integration Keynote – Novel Materials
Mr. Gary Dickerson, CEO, Applied Materials

12:30 PM

Materials and Integration ("Page 3") – Framework for Novel Compute (FRANC)

1:15 PM


“Perhaps newly devised design automation procedures could translate from logic diagram to technological realization with any special engineering.”
—Gordon Moore, 1965

Can we dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialization and innovation?

2:30 PM

Design Keynote
Dr. Aart de Geus, Co-CEO & Chairman, Synopsys

3:00 PM

Design – Circuit Realization At Faster Timescales (CRAFT)

3:45 PM

Design ("Page 3") – Intelligent Design of Electronic Assets (IDEA)

4:30 PM

Design ("Page 3") – Posh Open Source Hardware (POSH)

5:15 PM


Wednesday, July 25, 2018

7:30 AM

Partnership Breakfast
Networking and poster session

9:30 AM

Opening Keynote
Dr. Bill Dally, Chief Scientist & Senior VP, NVIDIA

“…we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array.” —Gordon Moore, 1965

Can we enjoy the benefits of specialized circuitry while still relying on general programming constructs through the proper software/hardware co-design?

10:00 AM

Architectures – Hierarchical Identify Verify Exploit (HIVE)

10:30 AM

Architectures ("Page 3") – Software Defined Hardware (SDH)

11:00 AM

Architectures ("Page 3") – Domain-specific System on Chip (DSSoC)

12:00 PM


Discover the applications that will determine the next generation of electronics.

1:15 PM

Applications Keynote
Dr. Wally Rhines, CEO, Mentor Graphics

1:45 PM

Applications|Sensors – Near Zero Power RF and Sensor Operations (N-ZERO)

2:15 PM

Applications|Sensors – Reconfigurable Imaging (ReImagine)

2:45 PM


3:15 PM

Applications|Security – System Security Integrated Through Hardware and Firmware (SSITH)

3:45 PM

Applications|Security – Supply Chain Hardware Integrity for Electronics Defense (SHIELD)

4:15 PM

Applications|Learning – Spectrum Collaboration Challenge (SC2)

4:45 PM

Applications|Learning – Lifelong Learning Machines (L2M)

5:15 PM

Where Do We Go From Here?
DARPA Program Managers will discuss the challenges and opportunities facing future technologies

6:15 PM