Summit
Agenda

DARPA ERI Summit

July 23-25  |  San Francisco, CA

Monday, July 23, 2018

7:30 AM

Workshop Check-In / Breakfast (There will be no on-site registration) 

8:30 AM

ERI “What’s Next” Technical Brainstorming Workshops
Hardware for Next Generation AI (8:30am – 12:30pm)
Hardware Security (8:30am – 12:30pm)  
Hardware Emulation (8:30am – 12:30pm)
Integrated Photonics (8:30am – 12:30pm)

12:30 PM

Workshops Adjourn

1:30 PM

Summit Check-In

2:30 PM

Welcome and Announcement of ERI "Page 3" Teams
Dr. Jay Lewis, Deputy Director, Microsystems Technology Office, DARPA

3:15 PM

Introduction of Joint University Microelectronics Program (JUMP) Focus Areas
Dr. Linton Salmon, Program Manager, DARPA MTO
Dr. Anthony Rowe, Associate Professor, Electrical & Computer Engineering, Carnegie Mellon University
Dr. Valeria Bertacco, Professor, Electrical Engineering, University of Michigan
Dr. Suman Datta, Freimann Chair of Engineering Professor, Notre Dame University
Dr. Kaushik Roy, Professor, Electrical & Computer Engineering, Purdue University
Dr. Mark Rodwell, Professor, Electrical & Computer Engineering, University of California, Santa Barbara
Dr. Tajana Rosing, Professor, Computer Science and Engineering, University of California, San Diego

4:30 PM

Science and Policy at the End of Moore's Law
Dr. Erica Fuchs, Professor, Engineering and Public Policy, Carnegie Mellon University

5:00 PM

Impact of Commercial Partnership with the DoD
Mr. Tom Beckley, Senior Vice President & GM of Custom IC & PCB Group, Cadence Design Systems

5:30 PM

Reception and Networking

7:00 PM

Adjourn

Tuesday, July 24, 2018

7:00 AM

Check-In & Breakfast

8:00 AM

Opening Remarks and Introduction
Dr. William Chappell, Director, Microsystems Technology Office, DARPA

8:05 AM

Plenary
Dr. John Hennessy, Chairman, Alphabet

8:50 AM

The DARPA Mission
Dr. Steven Walker, DARPA Director

9:05 AM

The Electronics Resurgence Initiative
Dr. William Chappell, Director, Microsystems Technology Office, DARPA

9:35 AM

Break

“It may prove to be more economical to build large systems out of smaller functions, which are separately packaged and interconnected.”
—Gordon Moore, 1965

Can the integration of unconventional materials enhance conventional silicon circuits and continue the progress traditionally associated with scaling?

10:00 AM
10:30 AM

Common Heterogeneous Integration and Intellectual Property (IP) Reuse Strategies (CHIPS)
Mr. Andreas Olofsson, Program Manager, DARPA
Mr. Sergey Shumarayev, Senior Principal Engineer, Intel
Mr. Craig Hornbuckle, Chief Technology Officer, Jariet Technologies
Mr. Richard Kingdon, Chief Executive Officer, Micross

11:15 AM

Materials and Integration ("Page 3") – Three Dimensional Monolithic System-on-a-Chip (3DSoC)
Dr. Linton Salmon, Program Manager, DARPA
Dr. Max Shulaker, Assistant Professor, Electrical Engineering & Computer Science, Massachusetts Institute of Technology
Dr. Subhasish Mitra, Professor, Electrical Engineering & Computer Science, Stanford University

12:00 PM

Materials and Integration Keynote – Novel Materials
Mr. Gary Dickerson, CEO, Applied Materials

12:30 PM

Materials and Integration ("Page 3") – Framework for Novel Compute (FRANC)
Dr. Young-Kai Chen, Program Manager, DARPA
Mr. Steve Pawlowski, Vice President, Advanced Computing Solutions, Micron
Dr. Naresh Shanbhag, Professor, Electrical & Computer Engineering, University of Illinois Urbana-Champaign

1:15 PM

Lunch

“Perhaps newly devised design automation procedures could translate from logic diagram to technological realization with any special engineering.”
—Gordon Moore, 1965

Can we dramatically lower the barriers to modern system-on-chip design and unleash a new era of circuit and system specialization and innovation?

2:30 PM

Design Keynote
Dr. Aart de Geus, Co-Chief Executive Officer & Chairman, Synopsys

3:00 PM

Design – Circuit Realization At Faster Timescales (CRAFT)
Dr. Linton Salmon, Program Manager, DARPA
Dr. Elad Alon, Professor, Electrical Engineering & Computer Sciences, University of California, Berkeley
Dr. Brucek Khailany, Director, ASIC & VLSI Research, NVIDIA

3:45 PM

Design ("Page 3") – Intelligent Design of Electronic Assets (IDEA) & Posh Open Source Hardware (POSH)
Mr. Andreas Olofsson, Program Manager, DARPA MTO
Dr. David White, Senior Director of Research & Development, Cadence Design Systems
Dr. Andrew Kahng, Professor, Computer Science & Engineering, University of California, San Diego
Dr. Clark Barrett, Associate Professor, Computer Science, Stanford University
Mr. Peter Ryser, Senior Director, System Software, System Integration and Validation, Xilinx
Mr. Christopher Tice, Vice President, Verification Continuum Solutions, Synopsys

5:15 PM

Broader Defense Department Technology Directions
Ms. Kristen Baldwin, Acting Deputy Assistant Secretary of Defense for Systems Engineering

5:30 PM

Adjourn

Wednesday, July 25, 2018

7:00 AM

Check-in & Breakfast

7:30 AM

Networking and Poster Session

9:30 AM

Opening Keynote
Dr. Bill Dally, Chief Scientist & Senior Vice President, NVIDIA

“…we could amortize the engineering over several identical items, or evolve flexible techniques for the engineering of large functions so that no disproportionate expense need be borne by a particular array.” —Gordon Moore, 1965

Can we enjoy the benefits of specialized circuitry while still relying on general programming constructs through the proper software/hardware co-design?

10:00 AM

Architectures – Hierarchical Identify Verify Exploit (HIVE)
Mr. Wade Shen, Program Manager, DARPA
Dr. Joshua Fryman, Senior Principal Engineer, Intel
Dr. Shekhar Borkar, Senior Director, Technology, Qualcomm

10:30 AM

Architectures ("Page 3") – Software Defined Hardware (SDH)
Mr. Wade Shen, Program Manager, DARPA
Dr. Luca Carloni, Professor, Computer Science, Columbia University
Dr. Suresh Jagannathan, Professor, Computer Science, Purdue University

11:00 AM

Architectures ("Page 3") – Domain-Specific System on Chip (DSSoC)
Dr. Tom Rondeau, Program Manager, DARPA
Dr. Pradip Bose, Distinguished Research Staff Member & Manager, Efficient & Resilient Systems, IBM
Dr. Dan Bliss, Associate Professor, Electrical, Computer & Energy Engineering, Arizona State University

12:00 PM

Lunch

Discover the applications that will determine the next generation of electronics.

1:15 PM

Applications Keynote
Dr. Walden Rhines, Chief Executive Officer, Mentor Graphics

1:45 PM

Applications|Sensors – Near Zero Power RF and Sensor Operations (N-ZERO)
Dr. Troy Olsson, Program Manager, DARPA
Dr. Dennis Sylvester, Professor & Director, Michigan Integrated Circuits Laboratory, University of Michigan

2:15 PM

Applications|Sensors – Reconfigurable Imaging (ReImagine)
Dr. Whitney Mason, Program Manager, DARPA
Dr. Peter Grossman, Technical Staff, Quantum Information & Integrated Nanosystems Group, MIT Lincoln Laboratory
Dr. Saibal Mukhopadhyay, Professor, Electrical & Computer Engineering, Georgia Institute of Technology

2:45 PM

Break

3:15 PM

Applications|Security – System Security Integrated Through Hardware and Firmware (SSITH)
Dr. Linton Salmon, Program Manager, DARPA
Dr. Joseph Kiniry, Principal Scientist, Galois

3:45 PM

Applications|Security – Supply Chain Hardware Integrity for Electronics Defense (SHIELD)
Mr. Kerry Bernstein, Program Manager, DARPA
Dr. Michael Kane, Senior Principal Research Scientist, SRI International
Dr. Christopher Lantman, Director, Program Development, Advanced Technology & Systems Division, SRI International

4:15 PM

Applications|Learning – Spectrum Collaboration Challenge (SC2)
Mr. Paul Tilghman, Program Manager, DARPA
Dr. Greg Wright, Technical Staff, Wireless Technology Research, Nokia Bell Labs

4:45 PM

Applications|Learning – Lifelong Learning Machines (L2M)
Dr. Hava Siegelmann, Program Manager, DARPA
Dr. Hod Lipson, Professor, Mechanical Engineering & Data Science, Columbia University

5:15 PM

Where Do We Go From Here?
DARPA PMs will discuss the challenges and opportunities facing future technologies with an outbrief on the Workshops and Summit

6:15 PM

Adjourn